This invention relates to performing floating point arithmetic operations in programmable devices, such as programmable logic devices (PLDs), including the use of specialized processing blocks, which may be included in such devices, to perform floating point operations.
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., under the family name STRATIX® includes DSP blocks, each of which includes a plurality of multipliers (e.g., four 18-bit-by-18-bit multipliers). Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as individual multipliers, but also as four smaller multipliers, or as one larger multiplier (e.g., one 36-bit-by-36-bit multiplier in the case of four 18-bit-by-18-bit multipliers). In addition, e.g., one complex multiplication (which decomposes into two multiplication operations for each of the real and imaginary parts) can be performed. In order to support four 18-bit-by-18-bit multiplication operations, a block in a member of the aforementioned STRATIX® device family may have 4×(18+18)=144 inputs. Similarly, the output of an 18-bit-by-18-bit multiplication is 36 bits wide, so to support the output of four such multiplication operations, such a block would have 36×4=144 outputs.
The arithmetic operations to be performed by a PLD frequently are floating point operations. However, to the extent that known PLDs, with or without DSP blocks or other specialized blocks or structures, including the aforementioned STRATIX® family of PLDs, can perform floating point operations at all, they operate in accordance with the IEEE754-1985 standard, which requires that values be normalized at all times because it implies a leading “1”. However, that leads to certain inefficiencies as described below.